1. Field of the Invention
The present invention relates to a capacitor assembly and particularly to an MIM capacitor for integration into an integrated circuit, as well as a method for producing the capacitor assembly.
2. Description of the Related Art
Integrated circuits have capacitors as passive devices. Particularly high frequency circuits in BIPOLAR, BICMOS and CMOS technologies require integrated capacitors with a high specific capacitance at a high voltage linearity, with a precise capacitance value and with low parasitic capacitances. Conventionally, MOS and MIS capacitors, as well as MIM (MIM=Metal Isolator Metal) capacitors are used therefore. Conventional MOS and MIS capacitors, respectively, have, as a disadvantageous property a strong voltage dependency due to voltage-induced space charge regions as well as high parasitic capacitances as a result of a low distance of the capacitor assembly to a substrate whereon the capacitor assembly is disposed.
These problems can be avoided by using MIM capacitors. In integrated circuits, which have a multilayer metallization, MIM capacitors are possibly integrated without changing or influencing the adjacent metal traces. Compared to MOS and MIS capacitors, however, they have a significantly larger distance from the substrate.
DE 101 61 285 A1 presents already a concept, which is suitable for an integration of an MIM capacitor into a Cu Damascene technology. Thereby, the MIM capacitors can also have thin dielectric layers.
An MIM capacitor according to the prior art is illustrated in FIG. 5. A capacitor assembly is shown, which extends across three sheets 502, 504, 506 of an integrated circuit. The lower sheet 502 is separated from the middle sheet 504 by a separation layer 510, and the middle sheet 504 is separated from the upper sheet 506 by a separation layer 512. The separation layers 510, 512 are non-conductive diffusion barriers, such as of Si3N4.
In the following, the construction of the MIM capacitor assembly is described in Cu Dual Damascene architecture from bottom to top. The capacitor assembly has a lower electrode 522. The lower electrode 522 designed as a solid Cu plate is part of a conductive trace in the lower sheet 502. A conductive barrier layer 524, for example of TaN or TiN can be deposited on the lower electrode 522. The barrier layer 525 is disposed in the middle sheet 504. To connect the barrier layer 524 to the lower electrode 522, the separation layer 510 has an interruption. A dielectric layer 526 is disposed on the lower barrier layer 524, and directly on the lower electrode 522, respectively, when the lower barrier layer 524 is not present. A dielectric 526 consists, for example, of Si3N4, Ta2O5 or Al2O3. An upper electrode 528 is disposed on the dielectric 526, that has generally a sheet structure (not shown) consisting of conductive barriers and possibly a metallic layer arranged between them. An etch stop layer 530 is deposited on the upper electrode 528. The upper electrode 528 is electrically conductively connected through a via hole 534 to a conductive trace 536 which is disposed in the upper sheet 506. The whole capacitor assembly is embedded in sheets 502, 504, 506 in intermediate sheet dielectrics (not shown). When producing the structure shown in FIG. 5, the layer 510 is deposited on the lower sheet 502 consisting, for example, of an isolating layer or another suitable substrate, and an SiO2 layer is deposited on the same.
This layer sequence will then be structured and processed to form a window opening or recess in the layer sequence. Then, the layers 524, 526, 528, 530 are deposited and structured to obtain the structure shown in FIG. 5. An SiO2 layer is deposited on the structure formed in that way, the layer 510 is deposited thereon and the via hole 534 extends through the same.
It has turned out that with such a structure, capacitors with high quality requirements can be realized. The high quality results mainly from a low series resistance, which results mainly from the fact that the first electrode is integrated in the conductive trace level.
Integrated circuits often require small capacitances with high quality, such as for RF applications like filters, mixed signals or switches, but also within the same chip capacitances with a high total capacitance but lower quality requirements. Small capacitances can be produced according to the prior art. Capacitances with a large total capacitance, such as coupling capacitances, require, however, a high specific capacitance, which can be obtained by a large capacitance area and/or a thin dielectric.
This is problematic, since the dielectric of a capacitor arrangement according to the prior art has a relatively high defect density. The lower Cu electrode mainly causes the high number of defects. The lower electrode is heated during the production process. A heavy metal, such as copper, has a high diffusion constant, so that a diffusion of copper atoms into the adjacent dielectric occurs with the arising process temperatures. An impurity of the dielectric by Cu diffusion can lead to leaking currents up to short-circuits. A further disadvantage are roughnesses on the Cu surface, which are caused by Cu hillocks as well as scratches, and which lead to electronic field peaks and thus to a reduced electrical strength or also to leaking currents up to short-circuits. These negative effects stand in the way of the requirements of a large total capacitance, namely a thin dielectric as well as an increased capacitor area.
As a result of the mentioned effects, the quality of the capacitor assembly is reduced, which shows in a lower yield and a shorter life span, respectively. The reduced quality as well as the increased rejection rate results in increased production and follow-up costs.